Broadcom Second Generation Dual-Frequency GNSS chip - BCM47765

• Highest levels of navigation performance
• Industry-leading accuracy
• Supports HDGPS (High-Definition GPS) Broadcom technology
• Highest levels of urban multipath mitigation
• New multipath scanner hardware block
• Very low GNSS and sensor hub power consumption
• Small PCB footprint (saves 50% board space over discrete sensor hub + GNSS solutions)
• Optional on-chip PVT calculations
• Robust anti-spoofing behavior through hardware RPM (Receiver Power Monitoring) for L1 and L5

Features

• GNSS subsystem functions and interfaces including the following:
• A massively parallel search engine with separate tracking engines
• Internal LNAs and adjustable gain to support external LNA operation with a noise figure better than 3.5 dB across process, voltage and temperature – Standards support for AGPS applications, including GSM/UMTS/LTE (3GPP 44.031, 44.035, 25.331, and 36.355)
• Excellent transmit blocker performance allowing for a single filter on the BOM
• Enhanced autonomous acquisition: multiday, multi-constellation long-term orbit (LTO) data accelerates the acquisition of satellite signals.
• Synchronization pulse input enables the BCM47765 to be synchronized to an external timing reference or to provide precise GNSS time to another device
• A GNSS location library API with protocol engines for control-plane (RRLP and RRC) and user-plane (SUPL) interfaces
• Autonomous, MS-based, MS-assisted, and enhanced autonomous GNSS operation. Enhanced autonomous operation includes LTO data for the GPS, GLONASS, Galileo and BDS constellations
• Time-stamped GNSS data and a multisecond data buffer
• Supports geofencing, sensor batching, sensor fusion, and sensor navigation
• Arm-based 32-bit Cortex-M4F (CM4) CPU:
• Single-precision Floating Point Unit (FPU)
• Memory Protection Unit (MPU)
• 1.125 MB internal SRAM (single-cycle access at full speed)
• Accelerated Single Instruction Multiple Data (SIMD) and Digital Signal Processing (DSP) functions
• 1.25 Dhrystone MIPS/MHz with an operating frequency up to 150 MHz
• Arm-based Cortex
• M0 (CM0) operating at up to 75 MHz with 32 KB RAM to offload the CM4 and save power
• 1 MB ROM (includes the bootloader)
• High-speed system interface (to an applications processor):
• Serial streaming SPI slave (up to 50 MHz)
• Alternate UART system interface supports rates up to 3.2 Mb/s
•  Peripheral DMA (PDMA) channels for increased peripheral communications speed
• Up to 49 programmable GPIOs
• I2S master/slave interface
• Pulse Density Microphone (PDM) input
• Interfaces to a host applications processor and to sensors:
• SPI: Two master ports for peripherals (normal, dual, quad, up to 50 MHz) and one slave port for host communication.
• UART: Four ports for host and peripheral communication
• BSC: One I2C compatible port
• Integrated 12-bit, 2-channel ADC
• Timers:
• A watchdog timer
• A Real-time Clock (RTC) (42 bits, 32.768 kHz)
• Two general purpose 32-bit microsecond timers
• A 48-bit microsecond counter for better resolution timestamps than the RTC can provide
• Serial Wire Debug (SWD)
• One-Time Programmable (OTP) memory programmed in manufacturing contains the following unique information:
• Wafer lot
• Wafer number
• Wafer X-Y coordinates
• Automatic Test Equipment (ATE) version number\

Applications

• Smartphones
• Tablets
• Mobile accessories
• Wearables
• Digital cameras