Spirent AION Chip Design Verification Cadence 16 Port Subscription - AON-CD-V-CAD-016-SUB

Product Description

Spirent AION Chip Design Verification Cadence 16 Port Subscription - AON-CD-V-CAD-016-SUB

Growth in technology areas such as cloud computing, mobile edge computing, AI,and 5G are pushing the demand for network capacity. Network equipment andsemiconductor manufacturers need to keep up with the demand by delivering ultra-high-density devices powered by cutting-edge application-specific integrated circuit(ASIC) and system-on-a-chip (SoC) solutions.Post-silicon validations are no longer sufficient to meet the aggressive time-to-market and cost-efficiency requirements. Design issues found late in post-siliconvalidation can cost thousands of hours of wasted effort and have a negative impacttime-to-market. Access to scalable and accurate pre-silicon verification is becominga must have for networking ASIC and SoC designers.Spirent Chip Design Verification Solution is integrated and hosted together with EDAemulators. It is time-synced with EDA emulation clock for accurate and realistic Layer2-3 traffic generation and real-time results analysis.

Spirent Chip Design Verification Solution enables effective and efficient pre-siliconvalidation from 1G to 800G. It bridges gaps between pre-silicon and post-siliconverifications, and delivers significant cost savings to customers by identifying issuesearly in the chip design stages. Using the unified Spirent TestCenter test platform inall phases of silicon product lifecycle provides:

• Improved operational efficiency and reduced total cost of ownership with zerolearning curve

• More effective measurements and result analysis

• Reusability of test cases/scripts in pre-silicon verification and post-siliconvalidation